1. Field of the Invention
The present invention relates to a synchronous semiconductor device and, more specifically, to a synchronous semiconductor memory device capable of high speed operation.
2. Description of Background of Art
In a conventional memory, processing of an input address proceeds in most cases simultaneously with processing of data. Here, as to the time of processing until the data is written to a memory cell, the time necessary for processing an address is longer than the time necessary for data processing. Processing of address takes time as it involves complicated processes such as determination of the necessity of redundancy processing for repairing defective memory cell and internal re-addressing. This time limits operation performance of the chip.
FIG. 55 represents the conventional flow of address processing.
Referring to FIG. 55, at the time of writing, an externally input address and data are taken through an input buffer to the semiconductor memory device approximately at the same time. Thereafter, data is distributed to the memory array along a data path. The address, on the other hand, may be subjected to logic conversion or logical processing such as redundancy determination for repairing defect, if any, or a process for generating burst addresses. The time necessary for address processing increases as the process content becomes complicated. After the end of logical processing, decoding takes place for activating a selecting signal YS for column selection. By this time, the data has already been transmitted to the memory array. In other words, the data is kept waiting until the selecting signal YS is activated, and this wasteful wait time limits operation frequency of the chip.
Various and many forms of memories have been proposed to realize high speed operation in recent semiconductor memory devices. High speed operation is also demanded for address processing.